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M61047FP
Battery Protection Analog Front End (AFE) IC
REJ03F0005-0200 Rev.2.00 Mar 04, 2005
Description
The M61047FP is intended to be used as SB: Smart Battery. All functions needed for SB are packed to this M61047FP. The combination use with microcomputer such as M37517 will give various functions such as a detection of SB Remaining Capacity. The reset circuit and the linear regulator for Vcc/Vref of microcomputer are dedicated in M61047FP. So this will help easy design of power circuit design of SB.
Features
* * * * * * * * * * * All FETs are controlled by microcomputer Built-in low dropout series regulator for microcomputer Built-in battery voltage monitor circuit of each battery cell Built-in output selector, which outputs the voltage each selected battery cell Built-in discharge circuit of each battery cell Built-in voltage detection circuit of each battery cell Built-in FET OFF function controlled by microcomputer Various powers saving function to reduce total power dissipation 3-wire serial data transfer system for communication from microcomputer High Input Voltage Device (Absolute Maximum Rating: 33 V) CMOS monolithic IC
Application
* Smart Battery System
Block Diagram
VCC VIN12 CFET PCFET DFET
VREG
Series regulator
FET control circuit
DFETCNT CFETCNT RESET Reset circuit Battery cell voltage detection circuit
VIN1 VIN2 VIN3 VIN4 GND Battery cell 1-4 voltage analog output
CS CK DI Serial to Parallel conversion circuit
ANALOG
Multiplexer circuit
Rev.2.00 Mar 04, 2005 page 1 of 23
M61047FP
Pin Arrangement
CK DI ANALOG CFET DFET PCFET GND VREG VCC DFETCNT 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CS CFETCNT VIN1 VIN2 VIN3 VIN4 RESET VIN12 N.C. N.C.
(Top view) Package: PLSP0020JB-A (20P2F-A)
M61047FP
Pin Description
Pin No. 9 8 13 18 17 16 15 7 5 4 6 14 3 19 10 20 1 2 Pin Name VCC VREG VIN12 VIN1 VIN2 VIN3 VIN4 GND DFET CFET PCFET RESET ANALOG CFETCNT DFETCNT CS CK DI Function Power source pin. Power from charger or battery Linear-Regulator output for microcomputer Monitoring charger is connected or not Battery 1 + voltage input Battery 1 - voltage and Battery 2 + voltage input Battery 2 - voltage and Battery 3 + voltage input Battery 3 - voltage and Battery 4 + voltage input Ground and Battery 4 - voltage input Discharge FET-Drive Output. The Driver is turned off by Microcomputer Charge FET-Drive Output. The Driver is turned off by Microcomputer Pre-charge FET-Drive Output. The Driver is turned off by Microcomputer Reset signal output to RESET of Microcomputer Various Analog signal outputs to AD-input of Microcomputer Input of CFET and PCFET control signal from Microcomputer Input of DFET control signal from Microcomputer During low signal input to this CS, data input to DI is enabled Input of shift clock from Microcomputer. DI's input data is latched by low-to-high edge of this CK Input of 6-bit length serial data from Microcomputer
Rev.2.00 Mar 04, 2005 page 2 of 23
M61047FP
Absolute Maximum Ratings
Item Absolute maximum rating Supply voltage Power dissipation Operating temperature range Storage temperature range Symbol Vabs Vcc PD Topr1 Tstg Ratings 33 30 800 -20 to +85 -40 to +125 Unit V V mW C C Condition
Reference period CK
TSDI DI
THDI
TSCS CS
THCS
Figure 1 Interface Timing
Rev.2.00 Mar 04, 2005 page 3 of 23
M61047FP
Electrical Characteristics
(Ta = 25C, Vcc = 14 V, unless otherwise noted)
Block Total Item Supply voltage Supply current 1 Supply current 2 Supply current 3 Regulator Output voltage Linear regulation Symbol Vsup Isup Ips Ipd Vreg Vline Min. -- 35 20 -- 3.276 4.75 -- -- Load regulation Vload -- -- Reset Battery voltage detection Detection voltage Release voltage Input offset voltage Voltage gain Output source current Output sink current Detection voltage of battery cell Interface DI input H voltage DI input L voltage CS input H voltage CS input L voltage CK input H voltage CK input L voltage DI set-up time DI hold time CS set-up time CS hold time DFETCNT input H voltage DFETCNT input L voltage CFETCNT input H voltage CFETCNT input L voltage CFETCNT sink current Conditioning circuit VIN1 resistor VIN2 resistor VIN3 resistor VIN4 resistor Vdet- Vdet+ Voff Gamp Isource Isink Vmo_max VDIH VDIL VCSH VCSL VCKH VCKL TSDI THDI TSCS THCS VDCH VDCL VCCH VCCL ICCH RON1 RON2 RON3 RON4 2.6 2.9 31 0.594 75 150 4.7 Vreg-0.5 0 Vreg-0.5 0 Vreg-0.5 0 600 600 600 600 Vreg-0.5 0 Vreg-0.5 0 0.3 250 250 250 250 Typ. -- 75 45 -- 3.3 5.0 2 4 3 5 2.75 2.975 206 0.600 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 500 500 500 500 Max. 30 115 70 0.5 3.333 5.25 10 100 15 150 2.9 3.05 385 0.606 -- -- -- Vreg 0.5 Vreg 0.5 Vreg 0.5 -- -- -- -- Vreg 0.5 Vreg 0.5 2 1000 1000 1000 1000 Unit V A A A V V mV mV mV mV V V mV -- A A V V V V V V V ns ns ns ns V V V V A Circuit 1 1 1 1 2 2 2 2 2 2 3 3 4 4 5 5 2, 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 CFETCNT = 3.3V (Vreg-Voff1)/Gamp VREG = 3.3V Power save mode (Battery voltage detection: OFF) Power down mode VCC = 14V, Iout = 10mA VCC = 14V, Iout = 10mA VREG = 3.3V VCC = 6.0V to 24V, Iout = 10mA VREG = 5.0V VCC = 7.5V to 24V, Iout = 10mA VREG = 3.3V VCC = 6.0V, Iout = 50A to 10mA VREG = 5.0V VCC = 7.5V, Iout = 50A to 50mA VREG = 3.3V VREG = 3.3V Condition
Rev.2.00 Mar 04, 2005 page 4 of 23
M61047FP
Measurement Circuit
Measuring Ipd: OFF Except above: ON
Ipd, Ips, Isup A VCC
CFET
PCFET
DFET VIN12 VREG
Measuring Ipd: ON Except above: OFF
VIN1 VIN2 VIN3 VIN4
0.47F
DI CK CS Data input 0.5VVREG-0.5V
GND
ANALOG
Measurement circuit 1
CFET VCC VIN1 VIN2 VIN3 VIN4
PCFET
DFET VIN12 I (VREG) VREG 0.47F V
DI CK CS Data input 0.5VVREG-0.5V
GND
ANALOG
Measurement circuit 2
Rev.2.00 Mar 04, 2005 page 5 of 23
M61047FP
CFET VCC VIN1 VIN2 VIN3 VIN4
PCFET
DFET VIN12 VREG V RESET DI CK CS Data input 0.5VVREG-0.5V
GND
ANALOG
Measurement circuit 3
CFET VCC VIN1 V1 VIN2 V2 VIN3 V3 VIN4 V4 GND
PCFET
DFET VIN12 VREG 0.47F
DI CK CS ANALOG V Data input 0.5VVREG-0.5V
Measurement circuit 4
Rev.2.00 Mar 04, 2005 page 6 of 23
M61047FP
CFET VCC VIN1 V1 VIN2 V2 VIN3 V3 VIN4 V4 GND
PCFET
DFET VIN12 VREG 0.47F
DI CK CS Isink ANALOG A Isource Data input 0.5VVREG-0.5V
Measurement circuit 5
CFET VCC 14V VIN1 VIN2 VIN3 VIN4 CFETCNT DFETCNT A A GND
PCFET
DFET VIN12 VREG 3.3V
DI CK CS A ANALOG A A
Measurement circuit 6
Rev.2.00 Mar 04, 2005 page 7 of 23
M61047FP
CFET VCC A V1 A V2 A V3 A V4 GND VIN4 VIN3 VIN2 VIN1
PCFET
DFET VIN12 VREG 0.47F
DI CK CS ANALOG Data input 0.5VVREG-0.5V
Measurement circuit 7
Rev.2.00 Mar 04, 2005 page 8 of 23
M61047FP
Operation Description
M61047FP is developed for intelligent Li-ion battery pack such as SB in SBS. M61047FP is suitable for Smart Battery. Pair using with Microcomputer such as M37517 and small additional parts will give various functions such as battery remaining capacity detection. All functions are described as follows. Note: SBS: Smart Battery System introduced by Intel and Duracell SB: Smart Battery, which contains 3 or 4 series Li-ion battery cells. Voltage Detection Circuit of Each Li-ion Battery Cell M61047FP can output each battery cell's voltage of 3 or 4 series connection. Built-in buffer amplifier is monitoring each battery voltage. Series Regulator M61047FP contains low drop out series regulator. Microcomputer in SB does not need any additional voltage regulator. Usually, although series regulator is 3.3 V output, it is possible to change to 5 V output by register setup at the time of flash memory rewriting of microcomputer. Reset Circuit Vreg output voltage is checked by Reset circuit of M61047FP. Therefore, lower voltage of Vreg issues RESET signal to stop mull-function of microcomputer. Also, lower voltage after long time's left issues RESET signal to stop mullfunction of microcomputer. This function is useful for safety of long time's left battery. When charger is connected to SB, this circuit will check Vreg voltage, so if Vreg voltage is NOT enough high, this circuit remains low as for RESET signal to microcomputer. Conditioning Circuit M61047FP have a discharge circuit of each cells. It is available for drop of cell voltage for safety purpose. And to shorten the difference voltage among the cells. It can extend the battery pack life. Power Save Function M61047FP contains power save function to control several supply current. It can operate in the three state, usual mode, power save mode, and power down mode. These three modes can be changed by the command from a microcomputer, and can control the consumption current in each mode. 1. Usual mode It is in the state where all circuits are operating. 2. Power save mode In power save mode, consumption current is reduced by stopping voltage detection circuit, and outputting ALALOG output with GND level. If ANALOG output is changed to the battery voltage output or offset voltage output of each cell by the command from a microcomputer, it will change to usual mode. In addition, the regulator circuit is operating in a power save mode. 3. Power down mode In power down mode, all circuits will be stopped. The shift to power down mode and operation at the time of resume from power down mode are explained below using Figure 2.
Rev.2.00 Mar 04, 2005 page 9 of 23
M61047FP * Enter Power Down Mode Microcomputer issues power down command to M61047FP after microcomputer detects that battery voltage is too low. After this command, the DFET pin is set to 'high' and the VIN12 pin is pulled down by internal resistor to be set 'low' and series regulator are turned off. In the power down mode, the M61047FP operation is impossible. And CFET, DFET and PCFET are set to 'high'. (In this situation, discharging is forbidden.) At this time, supply current becomes max. 0.5 A, so drops of battery voltage is prevented. * Resume from Power Down Mode After entering Power Down mode, the series regulator will begin operation when charger is connected (VIN12 pin is high). The RESET will output low to high signal when Vreg is over reset level voltage. Microcomputer will begin operation and send command to resume M61047FP from power down mode.
VIN12
GND level in discharging
DFET
VCC
PCFET
CFET
FET control circuit
VREG
Series regulator
VIN1
DFETCNT CFETCNT RESET RESET circuit
CS CK DI Serial to pallarel conversion circuit
Figure 2 Function After Detecting Over-Discharge
Rev.2.00 Mar 04, 2005 page 10 of 23
M61047FP
Block Diagram Description
Battery Voltage Detection Circuit The M61047FP battery voltage detection circuit is shown in Figure 3. This circuit is composed of switch, buffer amplifier, reference voltage section and logic circuit. Microcomputer selects detecting voltage before logic circuit controls the connection of switches. This connection decides which cell voltage (Vbat1, Vbat2, Vbat3, Vbat4) should be output from Analog out pin. Besides offset voltage can be output. In Power Down mode, supply current in this block is close to zero because all switches are off. Note: Regard 100 s as the standard of settling time by voltage change in this block.
S11
VIN1
VBAT1
Switch control From Serial to Parallel conversion circuit
S22
VIN2
S21 VBAT2
Logic circuit
S32
VIN3
S31 VBAT3
-
To Multiplexer circuit
S42
VIN4
S41 S02 VREF S01 VBAT4
+
GND
Figure 3 Battery Voltage Detection Circuit Table 1 Turned on Switches
Function VBAT1_OUTPUT VBAT2_OUTPUT VBAT3_OUTPUT VBAT4_OUTPUT VBAT1_OFFSET VBAT2_OFFSET VBAT3_OFFSET VBAT4_OFFSET Turn on Switch (refer to Figure 3) S11, S22 S21, S32 S31, S42 S41, S02 S21, S22 S31, S32 S41, S42 S01, S02
Rev.2.00 Mar 04, 2005 page 11 of 23
M61047FP Analog Output Selector Analog output selector block is shown in Figure 4. The command from microcomputer determines whether GND is outputted to an analog terminal, or the voltage chosen in the battery voltage detection circuit is outputted. At the time of GND output, since the battery voltage detection circuit stops, M61047FP goes into power save mode.
From Serial to Parallel conversion circuit
Battery voltage detection circuit
ANALOG
Analog output selector
- +
VREF
Figure 4 Analog Output Selector
Rev.2.00 Mar 04, 2005 page 12 of 23
M61047FP Series Regulator Series regulator is shown in Figure 5. Pch MOS transistor is used for output driver. The output voltage can be adjusted by M61047FP itself. So the external resistor is not required. Usually, although series regulator is 3.3 V output, it is possible to change to 5 V output by register setup at the time of flash memory rewriting of microcomputer. Note: There is a diode put between Vcc and Vreg terminal to prevent the invert current from damaging this IC when Vcc Voltage is higher than Vreg voltage. So please always keep Vreg voltage lower than Vcc+0.3 V. Set a condenser on output to suppress input changes or load changes. In order to suppress input change and load change, please attach a 0.47 F capacitor to VREG output. Regard 10 ms as the standard of settling time by input change/load change/output change.
VCC
+ - VREG
VREF S51 S52
R1
R2
R3
GND
Switch control
Serial to Parallel conversion circuit
Figure 5 Series Regulator
Rev.2.00 Mar 04, 2005 page 13 of 23
M61047FP Reset Circuit The M61047FP reset circuit is shown in Figure 6. This circuit is composed of comparator, reference voltage section and breeder resistor. Hysterics is given to detection voltage and release voltage. The reset output is Nch open drain structure so the reset delay time depends on external CR value. The reset circuit monitoring Vreg output to prevent microcomputer abnormal operation when Vcc voltage goes down abnormally.
VREG
VREG
R1
+ - RESET
R2 VREF
Rh
GND
Figure 6 Reset Circuit
Rev.2.00 Mar 04, 2005 page 14 of 23
M61047FP Conditioning Circuit The M61047FP conditioning circuit is shown in Figure 7. This circuit is composed of switch, resistor and logic circuit. According to the serial data from microcomputer, the logic circuit can individually control the switches (S61, S62 ... etc.) to do individual cell discharge. Moreover, it is possible to also make from 1 cell to 4 cells discharge similarly by sending serial data two or more times.
VIN1
S61 VBAT1 R61
VIN2
S62 VBAT2 Switch control From Serial to Parallel conversion circuit R62
VIN3 Logic circuit
S63 VBAT3 R63
VIN4
S64 VBAT4 R64
GND
Figure 7 Conditioning Circuit
Rev.2.00 Mar 04, 2005 page 15 of 23
M61047FP
Resister Map
Address Table 2
Address Establishment Data Reset Battery voltage output FET control Multiplexer select Regulator Conditioning circuit Don't care Don't care D5 0 0 0 0 1 1 1 1 D4 0 0 1 1 0 0 1 1 D3 0 1 0 1 0 1 0 1 D2 -- -- -- -- -- -- -- -- Data D1 -- -- -- -- -- -- -- -- D0 -- -- -- -- -- -- -- -- Contents -- Refer to table 3 Refer to table 4 Refer to table 5 Refer to table 6 Refer to table 7 -- --
Data Table 3
D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1
Battery Voltage Output
D0 0 1 0 1 0 1 0 1 Name VBAT1_OUTPUT VBAT2_OUTPUT VBAT3_OUTPUT VBAT4_OUTPUT VBAT1_OFFSET VBAT2_OFFSET VBAT3_OFFSET VBAT4_OFFSET BAT1 voltage monitor BAT2 voltage monitor BAT3 voltage monitor BAT4 voltage monitor Offset voltage output at BAT1 monitor Offset voltage output at BAT2 monitor Offset voltage output at BAT3 monitor Offset voltage output at BAT4 monitor Function
Note: Analog terminal output GND level when system reset. (All switches for battery voltage detect circuit are turned off.) Regard 100s as the standard of settling time by each change of ANALOG output.
Table 4
D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1
FET Control
Function D0 0 1 0 1 0 1 0 1 Name FCNT_AH FCNT_PL FCNT_DL FCNT_CH FCNT_CL FCNT_DH FCNT_PH FCNT_AL CFET High High High High Low Low Low Low DFET High High Low Low High High Low Low PCFET High Low High Low High Low High Low
Note: CFET, DFET and PCFET terminal are high when system reset.
Rev.2.00 Mar 04, 2005 page 16 of 23
M61047FP Table 5
D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1
Multiplexer Control (Analog Output Control)
D0 0 1 0 1 0 1 0 1 Name MP_GND1 MP_RUN MP_GND2 MP_GND3 -- -- -- -- Function GND output Battery voltage output select GND output GND output Don't care Don't care Don't care Don't care Notes BAT1 voltage monitor All switches for battery voltage detect are OFF. BAT4 offset voltage
Note: Analog terminal output GND level when system reset. Regard 100s as the standard of settling time by each change of ANALOG output.
Table 6
D2 0 0 0 0 1 1 1 D1 0 0 1 1 0 0 1
Regulator
D0 0 1 0 1 0 1 0 Name VREG_33 VREG_OFF VREG_50 VREG_33 Don't care Don't care Don't care Function VREG = 3.3 V VREG = 0 V (Regulator turned off) VREG = 5.0 V VREG = 3.3 V Notes Power Down Command
1 1 1 Don't care Note: The regulator output 3.3 V when system reset. All functions of M61047FP are stopped. But if the charger is connected then M61047FP will not enter power down mode. Regard 20 ms as the standard of settling time by change of VREG output.
Table 7
D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1
Conditioning Circuit
Function D0 0 1 0 1 0 1 0 1 Name CD_OFF CD_RON11 CD_RON21 CD_RON31 CD_RON41 CD_RON12 CD_RON22 CD_RON32 BAT1_SW OFF ON Don't care Don't care Don't care ON Don't care Don't care BAT2_SW OFF Don't care ON Don't care Don't care Don't care ON Don't care BAT3_SW OFF Don't care Don't care ON Don't care Don't care Don't care ON BAT4_SW OFF Don't care Don't care Don't care ON Don't care Don't care Don't care
Note: Conditioning circuit is floating when system reset. By transmitting data two or more times, BAT1 to BAT4 arbitrary cells can be turned on simultaneously.
Rev.2.00 Mar 04, 2005 page 17 of 23
M61047FP Digital Data Format The block diagram of the serial to parallel conversion circuit of serial data transmission is shown in Figure 8, and a timing chart is shown in Figure 9, respectively. After setting CS terminal to Low, serial data is read into the inside of IC in an order from LSB (D0) synchronizing with the stand-up of CK terminal. If CS terminal is set to High when it inputs by 6 bits, the contents of a 6-bit shift register are latched to an internal latch circuit after serial to parallel conversion.
MSB DI CK
Last 6-bit shift register D5 D4 D3 Decoder D2 D1
First
LSB
D0
CS
Address
Latch MPX
Latch MPX
Latch MPX
FET control
Latch MPX
Vreg control
Latch MPX
Battery voltage output
Multiplexer Conditioning control control
Figure 8 Serial to Parallel Conversion Circuit
LSB DI D0 D1 D2 D3 D4 D5
MSB
CK
CS
Figure 9 Timing Chart
Direct FET Control It is possible to control direct FET by sending a signal to DFETCNT terminal or CFETCNT terminal other than serial data transmission from a microcomputer. If DFETCNT terminal is set to high, DFET terminal will be set to high, and if CFETCNT terminal is set to high, CFET terminal and PCFET terminal will be set to high. Priority is given to this function regardless of serial data communications.
Rev.2.00 Mar 04, 2005 page 18 of 23
M61047FP
Timing Chart
Charging Sequence
Battery voltage (V)
5 4 3 2 1 0 20 From bottom: Vbat1, Vbat2, Vbat3, Vbat4 Charging time Vbat4 reaches overcharge detect voltage
CFET (V)
15 10 5 0 20 Off during initialization Instruction from microprocessor Start of charging Instruction from microprocessor
End of charging
PCFET (V)
15 10 5 0 20 Off during initialization
Instruction from microprocessor Start of precharging
Instruction from microprocessor End of charging
DFET (V)
15 10 5 0 20 15 10 5 0 4 3 2 1 0 3 VREG Charger connected RESET Microprocessor operation start VIN_1 pin VCC pin Off during initialization Instruction from microprocessor Start of charging
VREG, RESET (V)
Battery voltage (V)
ANALOG (V)
2 1 0 Instruction from microprocessor
VBAT1 monitor
VBAT3 VBAT2 monitor monitor
VBAT4 monitor
Note: A constant voltage battery charger is used.
Rev.2.00 Mar 04, 2005 page 19 of 23
M61047FP Discharge Sequence
Battery voltage (V)
5 4 3 2 1 0 20 Discharge time Vbat4 reaches excess discharge detect voltage From top: Vbat1, Vbat2, Vbat3, Vbat4 Self-discharge time
CFET (V)
15 10 5 0 20 Instruction from microprocessor
PCFET (V)
15 10 5 0 20 Instruction from microprocessor
DFET (V)
15 10 5 0
Instruction from microprocessor Off in power-down mode
End of discharge
Battery voltage (V)
20 15 10 5 0 4 3 2 1 0 3 System stop VREG RESET Instruction from microprocessor VIN_12 pin Pulled down to ground potential when discharge prohibited VCC pin VIN_1 pin
VREG, RESET (V)
ANALOG (V)
VBAT1 monitor
2 1 0
VBAT2 VBAT3 VBAT4 monitor monitor monitor
Rev.2.00 Mar 04, 2005 page 20 of 23
M61047FP
Application Circuit
1k
+ terminal
10k
0.22F
6.8
VIN12 VREG 0.47F
DFET
VCC
PCFET
CFET VIN1
1k 0.22F VBAT1 1k VIN2
CS CK
0.22F VBAT2 1k
MCU M37517F8HP
DI RESET CFETCNT DFETCNT
M61047FP
VIN3 0.22F VBAT3 1k VIN4 0.22F VBAT4 GND
ANALOG
- terminal
Figure 10 Application Circuit for 4 Cell Battery
Rev.2.00 Mar 04, 2005 page 21 of 23
M61047FP
1k
+ terminal
10k
0.22F
6.8
VIN12 VREG 0.47F
DFET
VCC
PCFET
CFET VIN1
1k VIN2 CS CK 0.22F VBAT2 1k
MCU M37517F8HP
DI RESET CFETCNT DFETCNT
M61047FP
VIN3 0.22F VBAT3 1k VIN4 0.22F VBAT4 GND
ANALOG
- terminal
Figure 11 Application Circuit for 3 Cell Battery
Rev.2.00 Mar 04, 2005 page 22 of 23
M61047FP
Package Dimensions
JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JB-A Previous Code 20P2F-A MASS[Typ.] 0.1g
20
11
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1
Index mark
10
c
A2
A1
*2 D
Reference Symbol
Dimension in Millimeters Min 6.4 4.3 Nom 6.5 4.4 1.15 1.45 0 0.17 0.13 0 0.1 0.22 0.15 0.2 0.32 0.2 10 6.4 0.65 6.6 0.77 0.10 0.3 0.5 0.7 Max 6.6 4.5
D E
L
A
A2 A *3 e y bp Detail F A1 bp c
HE e y L
6.2 0.53
Rev.2.00 Mar 04, 2005 page 23 of 23
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Keep safety first in your circuit designs!
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